1. Field of the Invention
The present invention relates in general to a bootstrap circuit for bootstrapping an input signal to a high voltage level, and more particularly to a bootstrap circuit which is capable of bootstrapping the input signal to the high voltage level at a high speed.
2. Description of the Prior Art
A conventional bootstrap circuit is adapted to bootstrap a voltage to be charged on a bootstrap capacitor, using a parasitic capacitance of an NMOS transistor. In the NMOS transistor, a source is charged to a voltage level Vdd-Vt when a high logic signal is applied to a drain under the condition that a supply voltage Vdd is applied to a gate, where Vt is a threshold voltage of the NMOS transistor. Namely, the source of the NMOS transistor cannot be charged to the supply voltage level Vdd. In order to make up for such a defect, the conventional bootstrap circuit utilizes the parasitic capacitance of the NMOS transistor. However, the conventional bootstrap circuit has a disadvantage in that it has a time delay in bootstrapping the gate of the NMOS transistor when a large load amount is present in the source of the NMOS transistor. Such a problem with the conventional bootstrap circuit will hereinafter be described in detail with reference to FIG. 1.
Referring to FIG. 1, there is shown a circuit diagram of the conventional bootstrap circuit. As shown in this drawing, the conventional bootstrap circuit comprises an inverter I1 for inverting an input signal from an input node IN, a capacitor C.sub.L connected to an output node B, and an NMOS transistor T1 for transferring the input signal inverted by the inverter I1 to the capacitor C.sub.L through the output node B to charge the capacitor C.sub.L. The conventional bootstrap circuit further comprises a delay stage 11 for delaying the input signal from the input node IN for a predetermined time period, and an NMOS transistor T2 having a gate for inputting the supply voltage Vdd. The NMOS transistor T2 is driven by the supply voltage Vdd to transfer the input signal delayed by the delay stage 11 to a gate of the NMOS transistor T1 through a junction node A.
The operation of the conventional bootstrap circuit with the above-mentioned construction will hereinafter be described.
When the input signal from the input node IN is high in logic, a voltage Vdd-Vt appears on the junction node A. In response to the voltage Vdd-Vt on the junction node A, the NMOS transistor T2 is turned off, whereas the NMOS transistor T1 is turned on, thereby causing a voltage charged on the capacitor C.sub.L to be discharged to the inverter I1. As a result, a voltage on the output node B remains at its low state. Then, when the input signal from the input node IN is changed from high to low in logic, a high logic signal from the inverter I1 is charged on the capacitor C.sub.L connected to the output node B through the NMOS transistor T1. In this case, a voltage (Vdd-Vt)+.increment.V appears on the junction node A as it is bootstrapped by a parasitic capacitor Cgs of the NMOS transistor T1. As a result, the voltage on the capacitor C.sub.L is charged to the supply voltage level Vdd with no loss of a voltage corresponding to the threshold voltage Vt of the NMOS transistor T1.
However, the parasitic capacitor Cgs of the NMOS transistor T1 has no capacitance sufficient to bootstrap sufficiently the voltage on the junction node A. Also, the bootstrap operation based on the parasitic capacitor Cgs of the NMOS transistor T1 is very slow because it is advanced as the voltage on the output node B rises. Further, a time constant RC becomes large because the load capacitor C.sub.L generally has a very large capacitance, resulting in much time being required in charging the lead capacitor C.sub.L. In result, the same time delay is required in bootstrapping the voltage on the junction node A, resulting in a degradation in a data transfer speed.